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  • FIGS. 4A and 4B are a cross-sectional side view and a corresponding doping concentration view, respectively, illustrating an exemplary asymmetrically formed floating gate transistor used as a memory cell of a FLASH/EEPROM array, formed in accordance with the present invention without using an extra FLASH/EE mask pattern, and implanted by a single asymmetric halo implant from only one select direct
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