mples in which connections between bonding pads for selecting functions and bump lands are switched to each other, FIG. 19 is a plan view showing recognition marks and product names formed by the same wiring material as the material of the rerouting layers, FIGS. 20 to 22 and FIG. 24 are sectional views of main parts of chip areas showing the steps until the solder bump forming step, FIG. 23 is a