prov:value
| - In the vector processing unit of FIG. 3, when a vector, for example A , is read out from the vector register 1 and is supplied to the arithmetic circuit 3, at the 0-th cycle, which is assumed to be started at a certain time Tm, the vector elements A0, A1, A2 and A3 are read out simultaneously and then at the 1-st cycle the vector elements A4, A5, A6 and A7 are read out simultaneously.
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