cell MC, i.e. a pair of MIS's QL1 and QL2 for load resistance, a pair of MIS's Qd1 and Qd2 for drive, and a pair of MIS's Qt1 and Qt2 for selection are, respectively, arranged as having an offset structure (indicated by thick lines) and there exist circuits other than SRAM in the peripheral circuit of SRAM and the same semiconductor chip, MIS's constituting the logic circuits may be arranged as ha