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  • circuit;FIGS. 4a and 4b are a top view of the present invention as implemented in a CMOS integrated circuit;FIG. 5 is a cross section of the integrated circuit of FIGS. 4a and 4b taken along section line A--A.DESCRIPTION OF THE PREFERRED EMBODIMENTFIG. 1 illustrates a schematic of the prior art circuit 10 of which the present invention is an improvement.
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